The present invention relates to an information processing apparatus, and more particularly to an information processing apparatus including a main storage which has a plurality of storage spaces obtained by logically partitioning the main storage.
Generally, the main storage of an information processing apparatus provides a single linear storage space assigned with addresses starting from address "0" to the highest address covering the total memory capacity of the main storage.
In recent years, many cases have risen where a physically single information processing apparatus is logically partitioned into a plurality of information processing apparatus to configure a plurality of information processing systems, and each system is, e.g., alternately started in time division. In such a case, it is necessary for the main storage of the information processing apparatus to provide a single linear storage space to each logically partitioned information processing apparatus (hereinafter called a logical information apparatus). The single linear storage space is assigned addresses starting from address "0" to the highest address which is logically allocated to each logical information apparatus.
Realizing a plurality of independent storage spaces by using a physically single main storage, as described above, is called logical partition of the main storage.
The conventional technique of realizing logical partition of the main storage in an information processing apparatus is described in the specification of U.S. Pat. No. 4,459,661 and other Patents. According to this conventional technique, logical partition of the main storage is realized in a virtual computer environment. The characteristic features of this technique are summarized in the following four points.
(1) When each logically partitioned logical information processing apparatus accesses the main storage, the logical information processing apparatus sends its specific identification information as well as the main storage access address to the main storage. PA0 (2) The main storage has a plurality of register pairs, each including two registers called a base register and an upper limit register. PA0 (3) When one of logical information processing apparatus accesses the main storage, the main storage selects one pair from the plurality of base/upper-limit register pairs, in accordance with the identification information sent with the main storage access address. PA0 (4) The access operation to the main storage by the one logical information processing apparatus has the following restraints as a result of the information stored in the one pair of base/upper-limit registers selected at the above (3). PA0 (a) A base address stored in the base register is added to the main storage access address. PA0 (b) The addition result at the above (a) is compared with an upper limit address stored in the upper limit register. PA0 (c) If the comparison result at the above (b) indicates that the addition result at the above (a) does not exceed the upper limit address, the access operation to the main storage is permitted at the address obtained through addition at the above (a). If the addition result at the above (a) exceeds the upper limit address, the access operation to the main storage is inhibited so that the access is not executed. PA0 (1) The above-described conventional technique uses a comparator for checking the upper limit of the main storage access address. It is necessary for a comparator of this type to determine which is the larger or smaller between two values, i.e., the upper limit address and the main storage access address. It is therefore necessary to provide a great amount of hardware logics. The conventional technique is therefore associated with the problem of a necessity of a great number of hardware devices. PA0 (2) The above-described conventional technique has the restraint that the areas of the main storage to be allocated to respective logical information apparatus should be continuous. PA0 (1) An address comparison circuit is removed from the partition check mechanism for the logically partitioned main storage. Since realizing the address comparison circuit requires more than a few hardware logics, the arrangement without the address comparison circuit simplifies the hardware logics and reduces the cost thereof. PA0 (2) Empty areas dispersed within the main storage of the present invention can be allocated to one logical information processing apparatus, thereby eliminating the inconvenience associated with the conventional technique. According to the conventional technique, two or more discontinuous empty areas cannot be assigned to one logical information processing apparatus. Therefore, if several empty areas are present within the main storage, only one empty area of the several empty areas can be assigned to a logical information processing apparatus the remaining large capacity of empty areas cannot be used for that logical information processing apparatus. Further, a small area in the area within the main storage assigned to one logical information processing apparatus can be re-allocated to another logical information processing apparatus, providing more flexibility of the logical partition of the main storage. PA0 (1) First means for providing logical information processing apparatus identification information (hereinafter also simply called identification information) for identifying each of a plurality of logical information processing apparatus obtained by logically partitioning a single information processing apparatus. PA0 (2) Second means for storing the identification information provided by the first means, the identification information being provided in correspondence with each area of a plurality of areas obtained by partitioning the main storage. PA0 (3) Third means for reading the identification information during the main storage access operation by one logical information processing apparatus, the identification information being stored in correspondence with each area within the main storage at the main storage access address. PA0 (4) Fourth means for comparing, during the main storage access operation by the one information logical information processing apparatus, the identification information read with the third means with the identification information passessed by the one information processing apparatus assuming the main storage. PA0 (5) Fifth means for determining if the main storage access operation by the one information processing apparatus is allowed or not, on the basis of the comparison result by the fourth means. If access is not allowed, the main storage access operation is canceled by the fifth means. PA0 (1) It is possible to dispense with an address comparison circuit in the partition check mechanism for the logically partitioned main storage, so that the hardware logics can be simplified and the cost thereof can be reduced. PA0 (2) It is easy to allocate discontinuous empty areas dispersed within the main storage to one logical information processing apparatus, thereby realizing the flexible logical partition of the main storage and efficiently using the information processing apparatus.
In this manner, the above-mentioned conventional technique realizes logical partition of the main storage.
The above-described conventional technique, however, is associated with the following problems.
Such restraint is not desirable from the standpoint of efficient use of the main storage. For example, if the main storage has an empty capacity m and the empty areas are present continuously within the main storage, then all the empty capacity m can be allocated to one of the logical information processing apparatus. However, if the empty areas are not present continuously and dispersed in several areas, although the total empty capacity m is present within the main storage, only a capacity smaller than the capacity m can be assigned to one of the logical information processing apparatus.
In addition, such a constraint is not desirable from the standpoint of allocation flexibility of the main storage to each logical processing apparatus. For example, it is assumed that an area A within the main storage is assigned to one of the logical information processing apparatus. If, for some reason, the logical information processing apparatus thereafter causes a small area a within the assigned area A to be set off-line as viewed from the apparatus itself the off-line area a, although not used by the logical information apparatus, cannot be assigned to another logical information processing apparatus.
The above-described conventional technique therefore has the problems that it is difficult to efficiently use the main storage, and to improve the allocation flexibility of the main storage to respective logical information processing apparatus.